1. Technical Field
The embodiments described here relate to a semiconductor integrated circuit (IC) and a method of controlling the same and, more particularly, to semiconductor IC and a method of controlling the same including a delay locked loop (DLL) circuit.
2. Related Art
In general, a DLL circuit is commonly used to provide an internal clock signal that is led by a predetermined time interval in a phase more than a reference clock signal obtained by converting an external clock signal. The DLL circuit generates a phase difference between the internal clock signal used in a semiconductor IC and the external clock signal by delaying the internal clock signal due to a clock buffer and a transmission line, such that it can be used to solve a problem of long output data access time. The DLL circuit performs a function of controlling the phase of the internal clock signal to lead by predetermined time interval ahead of the external clock signal.
The DLL circuit includes a clock input buffer to buffer the external clock signal, thereby generating a reference clock signal. Then, the delay clock output through the delay line provides a delay value acquired by modeling delay amount by delay elements existing in a path transmitted up to a data output buffer to the delay clock signal to generate a feedback clock signal. The DLL circuit includes a phase detector to perform comparison and detecting a phase of the reference clock signal and the feedback clock signal, such that it generates a delay control signal to allow the delay line to control the delay amount provided to the reference clock signal to generate the delay clock signal. The phase detecting signal output from the phase detector includes information upon which phase of the reference clock signal and the feedback clock signal leads. According to the information, the delay line provides positive delay time or negative delay time to the reference clock signal.
However, in order to achieve a high speed operation of the semiconductor IC, the semiconductor IC tends to use higher frequency clock signals. Accordingly, the DLL circuit performs a delay fix operation for the high frequency clock signals. As a result, the reference clock signal and the feedback clock signal input to the phase detector within the DLL circuit become a high frequency clock signal, such that they have a very short period. In the DLL circuit using the high frequency clock signal, as described above, even when slight jitter components are included in the reference clock signal or the feedback clock signal when the phase detector compares and detects the phase, errors occur in the phase comparing and detecting results. In many instances, the clock signals generated inside the DLL circuit substantially include the jitter components. This can serve as a factor for degrading reliability of the phase comparison and detecting results. These errors degrade performance of the DLL circuit and increase a defect rate of a data output operation of the semiconductor IC including the DLL circuit.